Intel leans harder on RISC-V

Much like IBM after the PC architecture ran away from it and almost collapsed Big Blue’s highly profitable minicomputer and mainframe businesses, Intel has been through some soul-searching in the wake of Arm’s expansion from the world of cellular phones into just about everything else. 

Intel has moved from a company that sued relentlessly to try to maintain control of the instruction set architecture (ISA) that powered the PCs that crippled IBM’s original business to one that now sees or at least claims to see the advantages in an ISA that anyone can use to build their own processors. Intel is now one of RISC-V’s biggest fans, launching this week a programme to try to get more chip designers onboard with the architecture.

At the RISC-V Spring Week back in May, Gary Martz, senior director of Intel Foundry Services, claimed, “Meeting the needs of the growing RISC-V community is one of our key objectives. We share the same vision that a free and open ISA that is developed by a broad industry collaboration is needed… We want to help continue this work and that’s why we’re investing.”

Intel is far from alone in trying to give RISC-V a helping hand. The storage company Western Digital was quick to adopt the ISA and has provided its own design for a processor to the community as open-source. Google sees RISC-V as the foundation for a new generation of accelerators that can improve the performance and cut the intense power consumption of AI applications. And rather than try to develop those accelerators itself – though it has experience with its own Tensorflow chips – sees an open-source community as vital to those ambitions. That has led to Google financing low-volume chip-manufacturing projects through the US foundry SkyWater Technology as well as developing its own tools to make it easier for those with more software than hardware experience to design chips.

Microchip Technology, which has struggled to find a way into the 32-bit market from its strong base in 8-bit and 16-bit microcontrollers has become a big fan of RISC-V. The acquisition of Microsemi, which itself absorbed Actel some years earlier, has provided a way for chip designers to more easily prototype RISC-V designs in field-programmable gate arrays (FPGA). 

Intel also sees the FPGA as a crucial technology for promoting work on designs that incorporate RISC-V processor cores. The chipmaker bought Altera several years ago, incorporating the larger FPGAs into processor modules aimed at data-centre users. Now, as part of the Pathfinder for RISC-V programme launched on Tuesday (30 August 2022), Intel is promoting FPGAs as prototyping vehicles for ready-made processor cores it and others in the programme, such as Andes Technology, Chips Alliance, OpenHW Group and SiFive, have developed. 

Much like Google, Intel has adopted the approach that a software developer-friendly design environment is what is needed. “The adoption of RISC-V is at an inflexion point across multiple markets and applications, and Intel fully appreciates that a healthy software ecosystem is critical for this new ISA to be successful,” says Vijay Krishnan, general manager of RISC-V ventures at Intel.

The Pathfinder software is an integrated development environment (IDE) that incorporates tools from Intel itself as well as other suppliers, such as UK-based Imperas Software, which provides a high-speed instruction-set simulator so that designs can be prototyped in an entirely virtual domain before being moved to hardware. The company built a demonstration at the Design Automation Conference (DAC) where the simulator was able to run the game Quake on a reference model of a RISC-V processor core in more or less real time on a regular laptop.

Like Google, Intel sees even hobbyists as potentially valuable. The Pathfinder IDE comes in two forms. The Starter Edition is intended for the hobbyist, academia and research community and is available as a free download. The more extensive Professional Edition is the one that provides access to more of the cores and tools from partners and will need to be licensed individually to commercial players.

With the momentum building up behind RISC-V, the question naturally arises of whether Arm is running into trouble. It’s not looking good for the future given that accelerators are likely to become much more prevalent in silicon because of their better power efficiency, assuming the software tools to program them work well. However, with that power comes responsibility. Existing core suppliers such as Arm do a lot of verification work on their designs to ensure the cores work under all circumstances. 

Rupert Baines, chief marketing officer at Codasip, points out that users who roll their own cores based on the open-source ISA or who adopt the RTL from suppliers and then customise it have up to now not always been that careful to verify that the results work properly. Though it may run a simple program just fine, there are so many degrees of freedom in a processor core that many bugs can lurk hidden and rise up on a simple software change. Suppliers of finished cores that are not customised can do a lot more to pre-verify the design and guarantee they work. 

If a design team does not need an accelerator that is tightly integrated into a host processor, something like an Arm Cortex is going to do the job just fine and may be easier to deal with given so many engineers have experience with the architecture. But short of the RISC-V community flaming out, the direction of travel does look to be getting clearer. The one aspect of design that may protect incumbents like Arm is that the processor architecture itself is becoming less important in determining the performance of the overall system. It is much more how multiple processors interact with each other over an on-chip or in-system network. That’s an area that still needs work.